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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr16l580 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave may 2007 rev. 1.4.1 general description the xr16l580 (l580) is a 2.25 to 5.5 volt universal asynchronous receiver and transmitter (uart) with 5 volt tolerant inputs and a reduced pin count. it is pin-to-pin and software compatible to industry standard 16c450, 16c550, st16c580, st16c650a and xr16c850 uarts. it has 16 bytes of tx and rx fifos and is capable of operating up to serial data rate of 1 mbps at 2.25 volt supply voltage. the internal registers is compatible to the 16c550 register set plus enhanced registers for add itional features to support today?s high bandwidth data communication needs. the enhanced features include intel or motorola data bus interface to match your cpu interface, autom atic hardware and software flow control to prevent data loss, selectable rx and tx trigger levels for mo re efficient interrupt service, wireless infrared (irda) encoder/decoder for wireless applications and a unique power-save mode to increase battery operating time. the device comes in the 48-tqfp and very small 32-qfn, 28-qfn and 24-qfn packages in industrial temperature range. applications ? handheld terminals and tablets ? handheld computers ? wireless portable poin t-of-sale terminals ? cellular phones dataport ? gps devices ? personal digital assistants modules ? battery operated instruments features ? smallest full featured uart ? 2.25v to 5.5v supply voltage ? 5v tolerant inputs (except xtal1) ? intel/motorola bus select ? ?0 ns? address hold time (t ah and t adh ) ? pin and software compatible to industry standard 16c450, 16c550, st16c580, st16c650a and xr16c850 in the 48-tqfp package. ? 16-byte transmit fifo ? 16-byte receive fifo with errors flags ? selectable rx and tx fifo trigger levels ? automatic hardware (r ts/cts) flow control ? automatic software (xon/xoff) flow control ? up to 3.125 mbps data rate at 5v and 2 mbps at 3.3v and 1 mbps at 2.25v operation with external clock input ? infrared (irda) encoder/decoder ? complete modem interface ? power-save mode to conserve battery power ? sleep mode with wake-up interrupt ? small packages: 24-qfn (4x4x0.9mm), 28-qfn (5x5x0.9mm) and 32-qfn (5x5x0.9mm) ? compatible to standard 48-tqfp packages, without the following signals: ior, io w, cs1, cs2, txrdy#, rxrdy#, rclk, baudout#, op1# and op2# ? industrial temperature grade(-40 to +85 o c) f igure 1. b lock d iagram vcc xtal1 xtal2 crystal osc/buffer tx, rx, rts#, cts#, dtr#, dsr#, intel or motorola data bus interface uart 16 byte rx fifo brg ir endec tx & rx uart regs *5 v tolerant inputs (except for xtal1) gnugget_blk a2:a0 pwrsave 16 byte tx fifo ri#, cd# reset (reset#) d7:d0 iow# (r/w#) cs# int (irq#) ior# gnd (2.25 to 5.5 v) 16/68#
xr16l580 2 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 f igure 2. p ackages and p in o ut (24, 28 and 32- pin qfn p ackages ) vcc 24-pin qfn in intel bus mode 123456 d6 d7 rx tx d5 16/68# 11 12 7 10 8 9 xtal1 xtal2 iow# gnd pwrsv cs# 18 17 16 15 14 13 20 19 24 21 23 22 d2 d1 d0 vcc d3 d4 a0 a1 a2 ior# int reset vcc 28-pin qfn in intel bus mode 1234567 d6 d7 rx tx d5 16/68# cs# 13 14 9 12 10 11 8 21 20 19 18 17 16 15 a0 a1 a2 nc int rts# reset 26 25 24 27 23 22 28 d2 d1 d0 vcc d3 d4 cts# xtal1 xtal2 iow# gnd pwrsv ior# nc d2 d1 d0 vcc d3 d4 gnd 24-pin qfn in motorola bus mode 123456 d6 d7 rx tx d5 16/68# 11 12 7 10 8 9 18 17 16 15 14 13 20 19 24 21 23 22 xtal1 xtal2 r/w# gnd pwrsv cs# a0 a1 a2 nc irq# reset# gnd 28-pin qfn in motorola bus mode 1234567 d6 d7 rx tx d5 16/68# cs# 13 14 9 12 10 11 8 21 20 19 18 17 16 15 26 25 24 27 23 22 28 d2 d1 d0 vcc d3 d4 cts# xtal1 xtal2 r/w# gnd pwrsv nc nc a0 a1 a2 nc irq# rts# reset# 1 23456 78 24 23 22 21 20 19 ri# d6 d7 rx tx cs# reset rts# int dtr# a0 a1 a2 d4 d3 d2 d1 d0 vcc cts# 18 17 dsr# d5 16/68# vcc 32-pin qfn in intel bus mode cd# 32 31 30 29 28 27 26 25 11 12 13 14 15 16 9 10 xtal1 xtal2 iow# gnd ior# pwrsave nc nc 32 31 30 29 1 23456 78 24 23 22 21 20 19 11 12 13 14 15 16 9 10 ri# d6 d7 rx tx cs# xtal1 xtal2 r/w# gnd nc reset# rts# irq# dtr# a0 a1 a2 d4 d3 d2 d1 d0 vcc cts# 28 27 26 25 18 17 dsr# d5 16/68# pwrsave nc nc gnd 32- pin qfn in motorola bus mode cd#
xr16l580 3 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave f igure 3. p ackages and p in o ut (48-tqfp p ackage ) ordering in formation p art n umber p ackage o perating t emperature r ange d evice s tatus xr16l580il24 24-lead qfn -40c to +85c active xr16l580il28 28-lead qfn -40c to +85c active xr16l580il 32-lead qfn -40c to +85c active xr16l580im 48-lead tqfp -40c to +85c active 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 48-tqfp in motorola bus mode nc d5 d6 d7 nc nc rx tx nc nc cs# nc nc nc nc nc nc gnd nc r/w# xtal2 xtal1 pwrsave reset# nc dtr# rts# nc irq# nc a0 a1 a2 nc nc cts# dsr# cd# ri# vcc d0 d1 d2 d3 d4 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 48-tqfp in intel bus mode nc d5 d6 d7 nc nc rx tx nc nc cs# nc nc nc nc ior# gnd nc iow# xtal2 xtal1 reset nc dtr# rts# nc int nc a0 a1 a2 nc cts# dsr# cd# ri# vcc d0 d1 d2 d3 d4 pwrsave 16/68# 16/68# nc vcc gnd nc nc nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12
xr16l580 4 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 pin descriptions pin descriptions n ame 24- qfn p in # 28- qfn p in # 32- qfn p in # 48- tqfp pin# t ype d escription data bus interface a2 a1 a0 14 15 16 16 17 18 17 18 19 26 27 28 i address data lines [2:0]. these 3 address lines select one of the internal registers in uart channel a/b during a data bus transac - tion. d7 d6 d5 d4 d3 d2 d1 d0 4 3 2 24 23 22 21 20 4 3 2 28 27 26 25 24 5 4 3 1 32 31 30 29 4 3 2 47 46 45 44 43 i/o data bus lines [7:0 ] (bidirectional). ior# (nc) 13 13 14 19 i when 16/68# pin is at logic 1, the intel bus interface is selected and this input becomes read strobe (active low). the falling edge insti - gates an internal read cycle and re trieves the data byte from an internal register pointed by the ad dress lines [a2:a0], puts the data byte on the data bus to allow the host processor to read it on the ris - ing edge. when 16/68# pin is at logic 0, the motorola bus interface is selected and this input is not used. iow# (r/w#) 11 11 12 16 i when 16/68# pin is at logic 1, it selects intel bus interface and this input becomes write strobe (active low). the falling edge instigates the internal write cycle and the ri sing edge transfer s the data byte on the data bus to an internal register pointed by the address lines. when 16/68# pin is at logic 0, the motorola bus interface is selected and this input becomes read (logic 1) and write (logic 0) signal. cs# 7 7 8 11 i this input is chip select (act ive low) to enable the device. int (irq#) 17 19 20 30 o (od) when 16/68# pin is at logic 1 for intel bus interface, this output become the active high device in terrupt output. the output state is defined by the user through the software setting of mcr[3]. int is set to the active mode when mcr[3] is set to a logic 1. int is set to the three state mode when mcr[3] is set to a logic 0. see mcr[3]. when 16/68# pin is at logic 0 for mo torola bus interface, this output becomes the active low device interrupt output (open drain). an external pull-up resistor is required for proper operation. modem or serial i/o interface tx 6 6 7 8 o uart transmit data or infrared encoder data. standard transmit and receive interface is enabled when mcr[6] = 0. in this mode, the tx signal will be a logic 1 during reset or idle (no data). infrared irda transmit and receive interface is enabled when mcr[6] = 1. in the infrared mode, the inactive state (no data) for the infrared encoder/decoder interface is a logic 0. if it is not used, leave it unconnected.
xr16l580 5 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rx 5 5 6 7 i uart receive data or infrared receive data. normal receive data input must idle at logic 1 conditi on. the infrared receiver idles at logic 0. rts# - 20 21 32 o uart request-to-send (active low) or general purpose output. this output must be asserted prior to using auto rts flow control, see efr[6], mcr[1] and ier[6]. this pin is not available in the 24- qfn package. cts# - 22 24 38 i uart clear-to-send (active low) or general purpose input. it can be used for auto cts flow control, see efr[7], msr[4] and ier[7]. this input should be connected to vcc when not used. this pin is not available in the 24-qfn package. dtr# - - 22 33 o uart data-terminal-ready (active low) or general purpose output. this pin is not available in the 24-qfn and 28-qfn packages. dsr# - - 25 39 i uart data-set-ready (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. this pin is not available in the 24-qfn and 28-qfn packages. cd# - - 26 40 i uart carrier-detect (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. this pin is not available in the 24-qfn and 28-qfn packages. ri# - - 27 41 i uart ring-indicator (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. this pin is not available in the 24-qfn and 28-qfn packages. ancillary signals xtal1 9 9 10 14 i crystal or external clock input. this input is not 5v tolerant. xtal2 10 10 11 15 o crystal or buffered clock output. this output may be use to drive a clock buffer which can drive other device(s). pwrsave 8 8 9 13 i power-save (active high). this feat ure isolates the l580?s data bus interface from the host preventing other bus activities that cause higher power drain during sleep mode. see sleep mode with auto wake-up and power-save feature section for details. this pin has an internal pull-down resistor in the 48-tqfp package. the 32-qfn package does not have this pull-down resistor. 16/68# 1 1 2 1 i intel or motorola bus select. this pin has an internal pull-up resistor in the 48-tqfp package. the 32-qfn package does not have this resistor. when 16/68# pin is at logic 1, 16 or intel mode, the device will oper - ate in the intel bus type of interface. when 16/68# pin is at logic 0, 68 or motorola mode, the device will operate in the motorola bus type of interface. pin descriptions n ame 24- qfn p in # 28- qfn p in # 32- qfn p in # 48- tqfp pin# t ype d escription
xr16l580 6 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 n ote : pin type: i=input, o=output, i/o= input/output, od=output open drain. reset (reset#) 18 21 23 35 i when 16/68# pin is at logic 1 for intel bus interface, this input becomes reset (active high). wh en 16/68# pin is at logic 0 for motorola bus interface, this input becomes reset# (active low). a 40 ns minimum active pulse on this pin will reset the internal reg - isters and all outputs of the uart. the uart transmitter output will be held at logic 1, the receiver input will be ignored and outputs are reset during reset period (see uart reset conditions). vcc 19 23 28 42 pwr 2.25v to 5.5v power supply. all input pins, except xtal1, are 5v tolerant. gnd 12 12 13 18 pwr power supply common, ground. gnd center pad center pad center pad n/a pwr the center pad on the backside of the qfn package is metallic and should be connected to gnd on the pcb. the thermal pad size on the pcb should be the approximate size of this center pad and should be solder mask defined. the solder mask opening should be at least 0.0025" inwards from the edge of the pcb thermal pad. nc - 14, 15 15, 16 5, 6, 9, 10, 12, 17, 20- 25, 29, 31, 34, 36, 37, 48 - no connects. note that in motorola mode, the ior# pin becomes an nc pin. pin descriptions n ame 24- qfn p in # 28- qfn p in # 32- qfn p in # 48- tqfp pin# t ype d escription
xr16l580 7 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave 1.0 product description the xr16l580 (l580) is an enhanced 16c550 universal asynchronous receiver and transmitter (uart). its features set is compatible to the st16c580 device and additionally offers intel or motorola data bus interface and power-save to isolate the data bus interface duri ng sleep mode. hence, the l580 adds 2 more inputs: 16/ 68# and pwrsave pins. the xr16l580 can operate from 2.25v to 5.5v with 5 volt tolerant inputs. the configuration registers set is 16550 uart compatible for control, status and data transfer. also, the l580 has 16-bytes of transmit and receive fifos, automatic rt s/cts hardware flow control, automatic xon/xoff and special character software flow control, transmit and re ceive fifo trigger levels, infrared encoder and decoder (irda ver 1.0), programmable baud rate generator with a pre scaler of divide by 1 or 4. the l580 is fabricated using an advanced cmos process. enhanced features the l580 uart provides a solution that supports 16 byte s of transmit and receive fifo memory. the l580 is designed to work with low supply voltage and high perf ormance data communication systems, that require fast data processing time. increased performance is realized in the l580 by the transmit and receive fifos, fifo trigger level controls and automatic fl ow control mechanism. this allows the external processor to handle more networking tasks within a given time. this increases the service interval giving the external cpu additional time for other applications and reducing the overall uart interr upt servicing time. in addition, the l580 provides the power-save mode that drastically reduces the po wer consumption when the device is not used. the combination of the above greatly reduces the cpu?s bandwidth requirement, increases performance, and reduces power consumption. data bus interface, intel or motorola type the l580 provides a host interface that supports intel or motorola microprocessor (cpu) data bus interface. the intel bus compatible inte rface allows direct interconnect to inte l compatible type of cpus using ior#, iow# and cs# inputs for data bus operation. the motoro la bus compatible interface instead uses the r/w# and cs# signals for data bus transactions. see pin descri ption section for details on a ll the control signals. the intel and motorola bus interface selection is made through the pin, 16/68#. data rate the l580 is capable of operation up to 3.125 mbps at 5v, 2 mbps at 3.3v and 1 mbps at 2.5v supply with 16x internal sampling clock rate. the de vice can operate with an external 24 mhz crystal on pins xtal1 and xtal2, or external clock source of up to 50 mhz on xtal1 pin. with a typical crystal of 14.7456 mhz, all standard data rates of up to 921.6 kbps can be generated. internal enhanced register sets the l580 uart has a set of enhanced registers providing control and monitoring functions. interrupt enable/ disable and status, fifo enable/disa ble, selectable tx and rx fifo trigger levels, automatic hardware/ software flow control enable/disable, programmable b aud rates, infrared encoder/decoder enable/disable, modem interface controls and status, sleep mode and power-save mode are all standard features. following a power on reset or an external reset (and operating in 16 or intel mode), the registers defaults to the reset condition and its is compatible with previous gener ation of uarts, 16c450, 16c 550, 16c580, 16c650a and 16c850.
xr16l580 8 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 2.0 functional descriptions 2.1 cpu interface the cpu interface is 8 data bits wide with 3 address li nes and control signals to execute data bus read and write transactions. the l580 data interface supports the in tel compatible types of cpus and it is compatible to the industry standard 16c550 uart. no clock (oscillator nor external clock) is requir ed to operate a data bus transaction. each bus cycle is asynchronous using cs#, ior# and iow# or r/w# inputs. a typical data bus interconnection for intel and motorola mode is shown in figure 4 . f igure 4. xr16l580 t ypical i ntel /m otorola d ata b us i nterconnections vcc vcc a0 a1 a2 uart_cs# ior# iow# d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 cs# d0 d1 d2 d3 d4 d5 d6 d7 ior# iow# uart_int int serial interface of rs-232 or rs-422 intel data bus interconnections gnd uart_reset reset 16/68# ri# cd# dsr# cts# rts# dtr# rx tx pwrsave vcc vcc a0 a1 a2 uart_cs# r/w# d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 cs# d0 d1 d2 d3 d4 d5 d6 d7 ior# iow# uart_irq# int serial interface of rs-232 or rs-422 motorola data bus interconnections gnd uart_reset# reset ri# cd# dsr# cts# rts# dtr# rx tx pwrsave vcc 16/68#
xr16l580 9 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave 2.2 5-volt tolerant inputs the l580 can accept up to 5v inputs when operating at 3. 3v or 2.5v. but note that if the l580 is operating at 2.5v, its v oh may not be high enough to meet the requirements of the v ih of a cpu or a serial transceiver that is operating at 5v. note that the xtal1 pin is not 5v tolerant when external clock supply is used. 2.3 device hardware reset the reset or reset# input resets the internal registers and the serial in terface outputs in both channels to their default state (see table 11 ). an active pulse of longer than 40 ns duration will be requir ed to activate the reset function in the device. 2.4 device identification and revision the xr16l580 provides a device identification code and a device revision code to distinguish the part from other devices and revisions. to read the identification code from the part, it is required to set the baud rate generator registers dll a nd dlm both to 0x00 . now reading the content of the dlm will provide 0x01 to indicate xr16l580 and readin g the content of dll will provide the revisi on of the part; for example, a reading of 0x01 means revision a. 2.5 internal registers the l580 has a set of enhanced registers for contro l, monitoring and data loading and unloading. the configuration register set is compatible to those already available in the standard 16c550. these registers function as data holding registers (thr/rhr), interrupt status and contro l registers (isr/ier), a fifo control register (fcr), receive line status and control register s, (lsr/lcr), modem status and control registers (msr/ mcr), programmable data rate (clock) divisor regist ers (dll/dlm), and an user accessible scratchpad register (spr). beyond the general 16c550 features an d capabilities, the l580 offers enh anced feature regi sters (efr, xon1, xoff 1, xon1 and xoff2) that provide automatic rts and cts hardware flow control and xon/xoff software flow control. all the register functions are discussed in full detail later in ?section 3.0, uart internal registers? on page 22 . 2.6 dma mode the dma mode (a legacy term) refers to data block transfer operation. the dma mode affects the state of the rxrdy# and txrdy# output pins available in the orig inal 16c550. these pins are not available in the xr16l580. the dma enable bit (fcr bit-3) does not have any function in this device and can be a ?0? or a ?1?. 2.7 int (irq#) output the interrupt output changes according to the operating mode and enhanced features setup. table 1 and table 2 below summarize the operating behavior for the transmitter and receiver in the intel and motorola modes. also see figures 21 through 24 . t able 1: int (irq#) p in o peration for t ransmitter fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) int pin (16/68# = 1) 0 = one byte in thr 1 = thr empty 0 = fifo above trigger level 1 = fifo below trigger level or fifo empty irq# pin (16/68# = 0) 1 = one byte in thr 0 = thr empty 1 = fifo above trigger level 0 = fifo below trigger level or fifo empty
xr16l580 10 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 2.8 crystal or external clock input the l580 includes an on-chip oscillat or (xtal1 and xtal2) to generate a clock when a crystal is connected between the xtal1 and xtal2 pins of the device. alternat ively, an external clock can be supplied through the xtal1 pin. the cpu data bus does not require this clock for bus operation. the crystal oscillator provides a system clock to the baud rate generato rs (brg) section. xtal1 is the input to the osc illator or external clock input and xtal2 pin is the bufferred output which can be used as a clock signal for other devices in the system. please note that the input xtal1 is not 5v tolerant and therefore, the maximum voltage at the pin should be vcc when an external clock is supplied. for programming details, see ?programmable baud rate generator.? f igure 5. t ypical c rystal connections the on-chip oscillator is designed to use an industry standard micropro cessor crystal (p arallel resonant, fundamental frequency with 10-22 pf capacitance load, esr of 20-120 ohms and 100ppm frequency tolerance) connected externally between the xtal1 an d xtal2 pins (see figure 5). when vcc = 5v, the on- chip oscillator can oper ate with a crystal whose freque ncy is not greater than 24 mhz. on the other hand, the l580 can accept an external clock of up to 50mhz at xt al1 pin, with a 2k ohms pull-up resistor on xtal2 pin (as shown in figure 6 ). this translates to a maximum of 3.125mbps serial data rate at 5v. t able 2: int (irq#) p in o peration f or r eceiver fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) int pin (16/68# = 1) 0 = no data 1 = 1 byte 0 = fifo below trigger level 1 = fifo above trigger level irq# pin (16/68# = 0) 1 = no data 0 = 1 byte 1 = fifo below trigger level 0 = fifo above trigger level c1 22-47pf c2 22-47pf y1 1.8432 mhz to 24 mhz r1 0-120 (optional) r2 500k - 1m xtal1 xtal2
xr16l580 11 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave for further reading on the oscillator circuit please see the applicat ion note dan108 on the exar web site at http://www.exar.com. 2.9 programmable baud rate generator the l580 uart has its own baud rate generator (brg) with a prescaler. the prescaler is controlled by a software bit (bit-7) in the m cr register. this bit selects the prescaler to divide the input crystal or external clock by a factor of 1 or 4. the clock output of the prescale r goes to the brg. the brg further divides this clock by a programmable divisor (via dll and dlm registers) between 1 and (2 16 -1) to obtain a 16x sampling rate clock of the serial data rate. the sampling rate clock is used by the transmitter for data bit shifting and receiver for data sampling. the brg divisor defaults to the maximum baud rate (dll = 0x01 and dlm = 0x00) upon power up. programming the ba ud rate generator regi sters dlm and dll provides th e capability of selecting the operating data rate. table 3 shows the standard data rates availabl e with a 14.7456 mhz crystal or external clock at 16x sampling rate clock rate. when using a non-standard data rate crystal or external clock, the divisor value can be calculated fo r dll/dlm with the following equation. f igure 6. e xternal c lock c onnection for e xtended d ata r ate f igure 7. b aud r ate g enerator and p rescaler divisor (decimal) = (xtal1 clock frequency / prescaler) / (serial data rate x 16) 2k xtal1 xtal2 r1 vcc external clock vcc gnd xtal1 xtal2 crystal osc/ buffer mcr bit-7=0 (default) mcr bit-7=1 dll and dlm registers prescaler divide by 1 prescaler divide by 4 16x sampling rate clock to transmitter baud rate generator logic
xr16l580 12 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 t able 3: t ypical data rates with a 14.7456 mh z crystal or external clock o utput data rate mcr bit-7=1 o utput data rate mcr bit-7=0 ( default ) d ivisor for 16x clock (decimal) d ivisor for 16x clock (hex) dlm p rogram v alue (hex) dll p rogram v alue (hex) d ata r ate e rror (%) 100 400 2304 900 09 00 0 600 2400 384 180 01 80 0 1200 4800 192 c0 00 c0 0 2400 9600 96 60 00 60 0 4800 19.2k 48 30 00 30 0 9600 38.4k 24 18 00 18 0 19.2k 76.8k 12 0c 00 0c 0 38.4k 153.6k 6 06 00 06 0 57.6k 230.4k 4 04 00 04 0 115.2k 460.8k 2 02 00 02 0 230.4k 921.6k 1 01 00 01 0
xr16l580 13 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave 2.10 transmitter the transmitter section comprises of an 8-bit transmit shift register (tsr) and 16 bytes of fifo which includes a byte-wide transmit holding register (thr). tsr shifts out every data bit with the 16x internal clock. a bit time is 16 clock periods. the transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop -bit(s). the status of the fifo and tsr are reported in the line status register (lsr bit-5 and bit-6). 2.10.1 transmit holding re gister (thr) - write only the transmit holding register is an 8-bit register pr oviding a data interface to the host processor. the host writes transmit data byte to the thr to be converted in to a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least-si gnificant-bit (bit-0) becomes first data bit to go out. the thr is the input register to the transmit fifo of 16 bytes when fifo operation is enabl ed by fcr bit-0. every time a write operation is made to the thr, the fifo data pointer is automatically bumped to the next sequential data location. 2.10.2 transmitter operation in non-fifo mode the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit-5) is set when the data byte is transferred to tsr. thr flag can generate a transmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr beco mes completely empty. 2.10.3 transmitter operation in fifo mode the host may fill the transmit fifo with up to 16 bytes of transmit data. t he thr empty flag (lsr bit-5) is set whenever the fifo is empty. the thr empty flag can ge nerate a transmit empty interrupt (isr bit-1) when the amount of data in the fifo falls below its programmed trig ger level. the transmit empty interrupt is enabled by ier bit-1. the transmitter empty flag (lsr bit-6) is set when both the tsr and the fifo become empty. f igure 8. t ransmitter o peration in non -fifo m ode transmit holding register (thr) transmit shift register (tsr) data byte l s b m s b thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 16x clock
xr16l580 14 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 2.11 receiver the receiver section contains an 8-bit receive shift register (rsr) and 16 bytes of fifo which includes a byte-wide receive holding register ( rhr). the rsr uses the 16x clock fo r timing. on the falling edge of a start or a false start bit, an internal receiver counter star ts counting at the 16x clock ra te. after 8 clocks the start bit period should be at the cent er of the start bit. at this ti me the start bit is sampled and if it is still a logic 0 it is validated as a start bit. evaluating the start bit in th is manner prevents the receiver from assembling a false character. each of the data, parity and stop bits is samp led at the middle of the bit to prevent false framing. if there were any error(s), they are reported in the lsr regi ster bits 2-4. upon unloading the receive data byte from rhr, the receive fifo pointer is bumped and the erro r tags are immediately updated to reflect the status of the data byte in rhr register. rhr can generate a receive data ready interrupt upon receiving a character or delay until it reaches the fifo tr igger level. furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not re ceived for 4 word lengths as defined by lcr[1:0] plus 12 bits time. this is equivalent to 3.7-4.6 character times. the rhr interrupt is enabled by ier bit-0. 2.11.1 receive holding regi ster (rhr) - read-only the receive holding register is an 8-bit register that holds a receive data byte from the receive shift register. it provides the receive data interface to the host processor. the rhr register is part of the receive fifo of 16 bytes by 11-bits wide, the 3 extra bits are fo r the 3 error tags to be reported in lsr register. when the fifo is enabled by fcr bit-0, the rhr contains the first data character received by the fifo. after the rhr is read, the next character byte is loaded into the rhr and the errors associated with the current data byte are immediately updated in the lsr bits 2-4. f igure 9. t ransmitter o peration in fifo and f low c ontrol m ode transmit data shift register (tsr) transmit data byte transmit fifo 16x clock auto cts flow control (cts# pin) auto software flow control flow control characters (xoff1,2 and xon1,2 reg.) txfifo1 thr interrupt (isr bit-1): fifo is enabled by fcr bit-0=1 - when the tx fifo falls below the programmed trigger level, and - when the tx fifo becomes empty.
xr16l580 15 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave f igure 10. r eceiver o peration in non -fifo m ode f igure 11. r eceiver o peration in fifo and a uto rts f low c ontrol m ode receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo1 16x clock receive data characters data bit validation error tags in lsr bits 4:2 receive data shift register (rsr) rxfifo1 16x clock error tags (16-sets) error tags in lsr bits 4:2 16 bytes by 11-bit wide fifo receive data characters fifo trigger=8 example : rx fifo trigger level selected at 8 bytes data fills to 14 data falls to 4 data bit validation receive data fifo receive data receive data byte and errors rhr interrupt (isr bit-2) programmed for desired fifo trigger level. fifo is enabled by fcr bit-0=1 rts# de-asserts when data fills above the flow control trigger level to suspend remote transmitter. enable by efr bit-6=1, mcr bit-1. rts# re-asserts when data falls below the flow control trigger level to restart remote transmitter. enable by efr bit-6=1, mcr bit-1.
xr16l580 16 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 2.12 auto rts (hardware) flow control this feature is not available in the 24-qfn package since it does not have the rts# pin. automatic rts hardware flow control is used to prevent data overrun to the local receiver fifo. the rts# output is used to request remote unit to suspend/r esume data transmission. the auto rts flow control features is enabled to fit specific application requirement (see figure 12 ): ? enable auto rts flow control using efr bit-6. ? the auto rts function must be started by asserting rts# output pin (mcr bit-1 to logic 1 after it is enabled). if using the auto rts interrupt: ? enable rts interrupt through ier bit-6 (after setting efr bit-4). the uart issues an interrupt when the rts# pin makes a transition from low to high: isr bit-5 will be set to logic 1. 2.13 auto rts hysteresis the l580 has a new feature that provid es flow control trigge r hysteresis while maintaining compatibility with the st16c550 uart. with the auto rts function enabled, an interrupt is generated when the receive fifo reaches the programmed rx tr igger level. the rts# pin will not be forc ed to a logic 1 (rts off), until the receive fifo reaches one trigger level above the programmed trigger level in the trigger table ( table 8 ). the rts# pin will return to a logic 0 after the rx fifo is unloaded to one trigger leve l lower than the programmed trigger level. this is described in figure 12 . under the above described condit ions, the l580 will continue to accept data until the receive fifo gets full. the auto rt s function is initiated when the rts# output pin is asserted to a logic 0 (rts on). 2.14 auto cts flow control this feature is not available in the 24-qfn package since it does not have the cts# pin. automatic cts flow control is used to prevent data overrun to the remote receiver fifo. the cts# input is monitored to suspend/restart the local transmitter. the aut o cts flow control feature is selected to fit specific application requirement (see figure 12 ): ? enable auto cts flow control using efr bit-7. if using the auto cts interrupt: ? enable cts interrupt through ier bit-7 (after setting efr bit-4). the uart issues an interrupt when the cts# pin is de-asserted (high): is r bit-5 will be set to 1, and uart will suspend transmission as soon as the stop bit of the character in process is shifted ou t. transmission is resumed after the cts# input is re- asserted (low), indicating more data may be sent.
xr16l580 17 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave f igure 12. a uto rts and cts f low c ontrol o peration (n ot a vailable in 24-qfn p ackage ) the local uart (uarta) starts data transfer by asserting rtsa# (1). rtsa# is normally connected to ctsb# (2) of remote uart (uartb). ctsb# allows its transmitter to se nd data (3). txb data arrives and fills uarta receive fifo (4). when rxa data fills up to its receive fifo trigger le vel, uarta activates its rxa data ready interrupt (5) and con - tinues to receive and put data into its fifo. if interrupt se rvice latency is long and data is not being unloaded, uarta monitors its receive data fill level to match the upper thre shold of rts delay and de-assert rtsa# (6). ctsb# follows (7) and request uartb transmitter to suspend data transfer. ua rtb stops or finishes sending the data bits in its trans - mit shift register (8). when receive fifo data in uarta is unloaded to match the lower threshold of rts delay (9), uarta re-asserts rtsa# (10), ctsb# recognizes the change (11) and restarts its transmitter and data flow again until next receive fifo trigger (12). this same event applies to the reverse direction when uarta sends data to uartb with rtsb# and ctsa# controlling the data flow. rtsa# ctsb# rxa txb transmitter receiver fifo trigger reached auto rts trigger level auto cts monitor rtsa# txb rxa fifo ctsb# remote uart uartb local uart uarta on off on suspend restart rts high threshold data starts on off on assert rts# to begin transmission 1 2 3 4 5 6 7 receive data rts low threshold 9 10 11 receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor rtsb# ctsa# rxb txa inta (rxa fifo interrupt) rx fifo trigger level rx fifo trigger level 8 12 rtscts1
xr16l580 18 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 2.15 auto xon/xoff (software) flow control when software flow control is enabled ( see table 10 ), the l580 compares one or two sequential receive data characters with the programmed xon or xoff-1,2 charac ter value(s). if receive character(s) (rx) match the programmed values, the l580 will halt transmission (tx) as soon as th e current characte r has completed transmission. when a match occurs, the xoff (if enabled vi a ier bit-5) flag will be set and the interrupt output pin will be activated. following a suspension due to a ma tch of the xoff character, the l580 will monitor the receive data stream for a match to the xon-1,2 character. if a match is found, the l580 will resume operation and clear the flags (isr bit-4). reset initially sets the contents of the xon/xoff 8-bit flow control registers to a logic 0. following reset the user can write any xon/xoff value desired for software flow c ontrol. different conditions can be set to detect xon/ xoff characters ( see table 10 ) and suspend/resume transmissions. when double 8-bit xon/xoff characters are selected, the l580 compares two consecutive receiv e characters with two software flow control 8-bit values (xon1, xon2, xoff1, xoff2) and controls tx tran smissions accordingly. under the above described flow control mechanisms, flow control charac ters are not placed (stacked) in the user accessible rx data buffer or fifo. in the event that the receive buffer is overfilling and flow control needs to be executed, the l580 automatically sends an xoff message (when enabled) via the serial tx output to the remote modem. the l580 sends the xoff character(s) two-character-times (= time taken to send two characters at the programmed baud rate) after the receive fifo crosses th e programmed trigger level. to clear this condition , the l580 will transmit the programmed xon character(s) as soon as receive fifo is less than one trigger level below the programmed trigger level (see table 8 ). the table below describes this. * after the trigger level is reached, an xoff character is se nt after a short span of time (= time required to send 2 characters); for example, after 2.083ms has elapsed for 9600 baud and 8-bit word length, no parity and 1 stop bit setting. 2.16 special character detect a special character detect feature is provided to detect an 8-bit character when bit-5 is set in the enhanced feature register (efr). when this character (xoff2) is detected, it will be placed in the fi fo along with normal incoming rx data. the l580 compares each incoming receive character with the programmed xoff-2 data. if a match exists, the received data will be transferre d to the rx fifo and isr bit-4 will be set to indicate detection of special character. although the internal register table show s xon, xoff registers with eight bits of character information, the actual number of bits is dependent on the programmed word length. line control register (lcr) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. the word length selected by lcr bits 0-1 also de termines the number of bits that will be used for the special character comparison. bit-0 in the xon, xoff registers corr esponds with the lsb bit for the receive character. t able 4: a uto x on /x off (s oftware ) f low c ontrol rx t rigger l evel int p in a ctivation x off c haracter ( s ) s ent ( characters in rx fifo ) x on c haracter ( s ) s ent ( characters in rx fifo ) 1 1 1* 0 4 4 4* 1 8 8 8* 4 14 14 14* 8
xr16l580 19 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave 2.17 infrared mode the l580 uart includes the infrared encoder and decoder compatible to the irda (infrared data association) version 1.0. the irda 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide high- pulse for each ?0? bit in the transmit data stream. this signal encoding reduces the on-time of the infrared led, hence reduces the power consumption. see figure 13 below. the infrared encoder and decoder are enabled by setting mcr register bit-6 to a ?1?. when the infrared feature is enabled, the transmit data output, tx, idles at logic zero level. likewise, the rx input assumes an idle level of logic zero from a reset and power up, see figure 13 . typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the rx pin. each time it senses a light pulse, it returns a logic 1 to the data bit stream. however, this is not true with some infrared modules on the market which indicate a logic 0 by a light pulse. so the l580 has a provision to invert the input polarity to accommoda te this. in this case, the user can enable mcr bit-2 to invert the ir signal at the rx pin. f igure 13. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding character data bits start stop 0000 0 11 111 bit time 1/16 clock delay irdecoder - rx data receive ir pulse (rx pin) character data bits start stop 0000 0 11 111 tx data transmit ir pulse (tx pin) bit time 1/2 bit time 3/16 bit time irencoder-1
xr16l580 20 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 2.18 sleep mode with wake-up interrupt and power-save feature the l580 supports low voltag e system designs, hence, a sleep mode with wake-up interrupt and power-save feature is included to reduce power consumption when the device is not actively used. 2.18.1 sleep mode all of these conditions must be sati sfied for the l580 to enter sleep mode: no interrupts pending (isr bit-0 = 1) the 16-bit divisor programmed in dlm and dll registers is a non-zero value sleep mode is enabled (ier bit-4 = 1) modem inputs are not toggling (msr bits 0-3 = 0) rx input pin is idling at a logic 1 the l580 stops its crystal oscillator to conserve power in the sleep mode . user can check the xtal2 pin for no clock output as an indication that the device has entered the sleep mode. the l580 resumes normal operation by any of the following: a receive data start bit transition (logic 1 to 0) at the rx input pin a data byte is loaded to the transmitter, thr or fifo a change of logic state on any of the modem or general purpose serial inputs: cts#, dsr#, cd#, ri# if the l580 is awakened by any one of the above conditions, it issues an interrupt as soon as the oscillator circuit is up and running and the device is ready to transmit/receive. this interrupt has the same encoding (bit- 0 of isr register = 1) as "no interr upt pending" and will clear when the isr re gister is read. this will show up in the isr register only if no other in terrupts are enabled. the l580 will retu rn to the sleep mode automatically after all interrupting condit ions have been serviced and cleared. if the l580 is awakened by the modem inputs, a read to the msr is required to re set the modem inputs. in any case, th e sleep mode will not be entered while an interrupt is pending. the l580 will stay in the sleep mode of operation until it is disabled by setting ier bit-4 to a logic 0. 2.18.2 power-save feature if the address lines, data bus lines, iow#, ior#, cs# and modem input lines remain steady when the l580 is in sleep mode, the maximum current will be in the microamp range as specified in the dc electrical characteristics on page 37 . if the input lines are floating or are toggling while the l580 is in sleep mode, the current can be up to 100 times more. if not using the power-save feature, an external buffer would be required to keep the address and data bus lines from toggling or floating to achieve the low current. but if the power- save feature is en abled (pwrsave pin connected to vcc), this will eliminate the nee d for an external buffer by internally isolating the address, data and control signals (s ee figure 1 on page 1) from other bus activities that could cause wasteful power drain. the l580 enters po wer-save mode when this pin is connected to vcc and the l580 is in sleep mode (see sleep mode section above). since power-save mode isolates the address, data and control signals, the device will wake-up only by : a receive data start bit transition (logic 1 to 0) at the rx input pin or a change of logic state on any of the modem or gen eral purpose serial inputs: cts#, dsr#, cd# or ri# the l580 will return to the power- save mode automatically after a re ad to the msr (t o reset the modem inputs) and all interrupting conditions have been servic ed and cleared. the l580 will stay in the power-save mode of operation until it is disabled by setting ier bit- 4 to a logic 0 and/or the power-save pin is connected to gnd.
xr16l580 21 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave 2.19 internal loopback the l580 uart provides an intern al loopback capability for system di agnostic purposes . the internal loopback mode is enabled by setting mcr register bit-4 to logi c 1. all regular uart functions operate normally including automatic hardware and software flow control. figure 14 shows how the modem port signals are re- configured. transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending. the tx pin is held at logic 1 or mark condition while rts# and dtr# are de-asserted, and ct s#, dsr# cd# and ri# inputs are ignored. caution: the rx input pins must be held to a logic 1 during loopback test else upon exiting the loopback test the uart may detect and report a false ?break? signal. f igure 14. i nternal l oop b ack tx rx modem / general purpose control logic internal data bus lines and control signals rts# mcr bit-4=1 vcc vcc transmit shift register (thr/fifo) receive shift register (rhr/fifo) cts# dtr# dsr# ri# cd# op1# rts# cts# dtr# dsr# ri# cd# vcc op2#
xr16l580 22 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 3.0 uart internal registers the l580 has a set of configuration registers selected by address lines a0, a1 and a2 with cs# asserted. the complete register set is shown on table 5 and table 6 . t able 5: uart internal registers a2,a1,a0 a ddresses r egister r ead /w rite c omments 16c550 c ompatible r egisters 0 0 0 rhr - receive holding register thr - transmit holding register read-only write-only lcr[7] = 0 0 0 0 dll - div latch low byte read/write lcr[7] = 1 0 0 1 dlm - div latch high byte read/write 0 0 0 drev - device revision code read-only dll, dlm = 0x00, lcr[7] = 1 0 0 1 dvid - device identification code read-only 0 0 1 ier - interrupt enable register read/write lcr[7] = 0 0 1 0 isr - interrupt status register fcr - fifo control register read-only write-only lcr 0xbf 0 1 1 lcr - line control register read/write 1 0 0 mcr - modem control register read/write lcr 0xbf 1 0 1 lsr - line status register reserved read-only write-only 1 1 0 msr - modem status register reserved read-only write-only 1 1 1 spr - scratchpad register read/write lcr 0xbf e nhanced r egisters 0 1 0 efr - enhanced function register read/write lcr = 0xbf 1 0 0 xon-1 - xon character 1 read/write 1 0 1 xon-2 - xon character 2 read/write 1 1 0 xoff-1 - xoff character 1 read/write 1 1 1 xoff-2 - xoff character 2 read/write
xr16l580 23 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave . t able 6: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 16c550 compatible registers 0 0 0 rhr rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=0 0 0 0 thr wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier rd/wr 0/ 0/ 0/ 0/ modem stat. int. enable rx line stat. int. enable tx empty int enable rx data int. enable cts int. enable rts int. enable xoff int. enable sleep mode enable 0 1 0 isr rd fifos enabled fifos enabled 0/ 0/ int source bit-3 int source bit-2 int source bit-1 int source bit-0 lcr 0xbf int source bit-5 int source bit-4 0 1 0 fcr wr rx fifo trigger rx fifo trigger 0/ 0/ dma mode enable tx fifo reset rx fifo reset fifos enable tx fifo trigger tx fifo trigger 0 1 1 lcr rd/wr divisor enable set tx break set par - ity even parity parity enable stop bits word length bit-1 word length bit-0 1 0 0 mcr rd/wr 0/ 0/ 0/ internal loop - back enable int out - put enable (op2#) (op1#) rts# output control dtr# output control lcr 0xbf brg pres - caler ir mode enable xonany invert ir rx 1 0 1 lsr rd rx fifo global error thr & tsr empty thr empty rx break rx fram - ing error rx parity error rx over - run error rx data ready 1 1 0 msr rd cd# input ri# input dsr# input cts# input delta cd# delta ri# delta dsr# delta cts# 1 1 1 spr rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr 0xbf baud rate generator divisor 0 0 0 dll rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=1 0 0 1 dlm rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 drev rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=1 dll=0x00 dlm=0x00 0 0 1 dvid rd 0 0 0 0 0 0 0 1
xr16l580 24 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 4.0 internal register descriptions 4.1 receive holding register (rhr) - read- only see?receiver? on page 14. 4.2 transmit holding register (thr) - write-only see?transmitter? on page 13. 4.3 baud rate generator divisors (dll and dlm) - read/write the baud rate generator (brg) is a 16-bit counter that generates the data rate for the transmitter. the rate is programmed through registers dll and dlm which are on ly accessible when lcr bit-7 is set to ?1?. see?programmable baud rate genera tor? on page 11. 4.4 interrupt enable register (ier) - read/write the interrupt enable register (ier) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are r eported in the interrupt status register (isr). 4.4.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = 1) and receive inte rrupts (ier bit-0 = 1) are enabled, the rhr interrupts (see isr bits 2 and 3) status will reflect the following: a. the receive data available interrupts are issued to the host when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b. fifo level will be reflected in the isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared wh en the fifo drops below the trigger level. c. the receive data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is rese t when the fifo is empty. enhanced registers 0 1 0 efr rd/wr auto cts enable auto rts enable special char select enable ier [7:4], isr [5:4], fcr[5:4], mcr[7:5], mcr[2] soft- ware flow cntl bit-3 soft - ware flow cntl bit-2 soft - ware flow cntl bit-1 soft - ware flow cntl bit-0 lcr=0 x bf 1 0 0 xon1 wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 xon2 wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 0 xoff1 wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 xoff2 wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 t able 6: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment
xr16l580 25 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave 4.4.2 ier versus receive/transmit fifo polled mode operation when fcr bit-0 equals a logic 1 for fifo enable; rese tting ier bits 0-3 enables the xr16l580 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr or rx fifo. b. lsr bit-1 indicates an overrun error has occurred and that data in the fifo may not be valid. c. lsr bit 2-4 provides the type of receive data erro rs encountered for the data byte in rhr, if any. d. lsr bit-5 indicates thr is empty. e. lsr bit-6 indicates when both the transmit fifo and tsr are empty. f. lsr bit-7 indicates a data error in at least one character in the rx fifo. ier[0]: rhr interrupt enable the receive data ready interrupt will be issued when rhr has a data characte r in the non-fifo mode or when the receive fifo has reached the programmed trigger level in the fifo mode. ? logic 0 = disable the receive data ready interrupt (default). ? logic 1 = enable the receiver data ready interrupt. ier[1]: thr interrupt enable this bit enables the transmit ready interrupt which is issued whenever the thr becomes empty in the non- fifo mode or when data in the fifo fa lls below the programmed trigger level in the fifo mode. if the thr is empty when this bit is enabled , an interrupt will be generated. ? logic 0 = disable transmit ready interrupt (default). ? logic 1 = enable transmit ready interrupt. ier[2]: receive line status interrupt enable if any of the lsr register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in fifo. lsr bit-1 generates an interrupt immediately when the character has been received. lsr bits 2-4 generate an in terrupt when the character with errors is read out of the fifo. ? logic 0 = disable the receiver line status interrupt (default). ? logic 1 = enable the receiver line status interrupt. ier[3]: modem status interrupt enable ? logic 0 = disable the modem status register interrupt (default). ? logic 1 = enable the modem status register interrupt. ier[4]: sleep mode enable (requires efr bit-4 = 1) ? logic 0 = disable sleep mode (default). ? logic 1 = enable sleep mode. see sleep mode section for further details. ier[5]: xoff interrupt enable (requires efr bit-4=1) ? logic 0 = disable the software flow cont rol, receive xoff interrupt. (default) ? logic 1 = enable the software flow control, receive xoff interrupt. see software flow control section for details.
xr16l580 26 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 ier[6]: rts# output interrupt enable (requires efr bit-4=1) this bit has no functionality in the 24-qfn package. ? logic 0 = disable the rts# interrupt (default). ? logic 1 = enable the rts# interrupt. the uart issues an interrupt when the rts# pin makes a transition from low to high. ier[7]: cts# input interrupt enable (requires efr bit-4=1) this bit has no functionality in the 24-qfn package. ? logic 0 = disable the cts# interrupt (default). ? logic 1 = enable the cts# interrupt. the uart issues an interrupt when cts# pin makes a transition from low to high. 4.5 interrupt status register (isr) - read-only the uart provides multiple levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will give the user the current hi ghest pending interrupt le vel to be serviced, others are queued up to be serviced next. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt source table, table 7 , shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources associated with each of these interrupt levels. 4.5.1 interrupt generation: ? lsr is by any of the lsr bits 1, 2, 3 and 4. ? rxrdy is by rx trigger level. ? rxrdy time-out is by a 4-char plus 12 bits delay timer. ? txrdy is by tx trigger level or tx fifo empty. ? msr is by any of the msr bits 0, 1, 2 and 3. ? receive xoff/special character is by det ection of a xoff or special character. ? cts# is when its transmitter toggles the input pin (from low to high) during auto cts flow control enabled by efr bit-7. ? rts# is when its receiver toggles the output pin (from low to high) during auto rts flow control enabled by efr bit-6. ? wake-up interrupt is when the device wakes up from sleep mode. see sleep mode section for more details. 4.5.2 interrupt clearing: ? lsr interrupt is cleared by reading the lsr register (but fifo error bit does not clear until the character(s) that generated the interrupt(s) is (are) read from the fifo). ? rxrdy interrupt is cleared by reading data until fifo falls be low the trigger level. ? rxrdy time-out interrupt is clea red by reading the rhr register. ? txrdy interrupt is cleared by reading the is r register or writing to the thr register. ? msr interrupt is cleared by reading the msr register. ? xoff interrupt is cleared by reading the is r or when xon character(s) is received. ? special character interrupt is cleared by reading the isr or after the next character is received. ? rts# and cts# flow control interrupts are cleared by reading the msr register. ? wake-up interrupt is cleared by reading the isr register.
xr16l580 27 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave ] isr[0]: interrupt status ? logic 0 = an interrupt is pending and the isr contents ma y be used as a pointer to the appropriate interrupt service routine. ? logic 1 = no interrupt pending (default condition) or wa ke-up interrupt. the wake-up interrupt is issued when the l580 has been awakened from sleep mode. isr[3:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority leve ls (see interrupt source table 7 ). isr[5:4]: interrupt status these bits are enabled when efr bit-4 is set to a logic 1. isr bit-4 indicates that the receiver detected a data match of the xoff character(s). note that once set to a logic 1, the isr bit-4 will stay a logic 1 until a xon character is received. isr bi t-5 indicates that cts# or rts# has changed state. isr[7:6]: fifo enable status these bits are set to a logic 0 when the fifos are disa bled. they are set to a logic 1 when the fifos are enabled. 4.6 fifo control register (fcr) - write-only this register is used to enable the fifos, clear the fifos, set the transm it/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: fcr[0]: tx and rx fifo enable ? logic 0 = disable the transmit and receive fifo (default). ? logic 1 = enable the transmit and receive fifos. this bit must be set to logic 1 when other fcr bits are written or they will not be programmed. fcr[1]: rx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no receive fifo reset (default) ? logic 1 = reset the receive fifo pointers and fifo le vel counter logic (the rece ive shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. t able 7: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of interrupt l evel b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 1 0 0 0 1 1 0 lsr (receiver line status register) 2 0 0 1 1 0 0 rxrdy (receive data time-out) 3 0 0 0 1 0 0 rxrdy (received data ready) 4 0 0 0 0 1 0 txrdy (transmit ready) 5 0 0 0 0 0 0 msr (modem status register) 6 0 1 0 0 0 0 rxrdy (received xoff or special character) 7 1 0 0 0 0 0 cts#, rts# change of state - 0 0 0 0 0 1 none (default) or wake-up interrupt
xr16l580 28 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 fcr[2]: tx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no transmit fifo reset (default). ? logic 1 = reset the transmit fifo pointers and fifo le vel counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[3]: dma mode select (legacy) this bit has no function and should be left at ?0?. fcr[5:4]: transmit fifo trigger select (?00? = default, tx trigger level = 1) these 2 bits set the trigger level for the transmit fifo. the uart will issue a transmit interrupt when the number of characters in the fifo falls below the selected trigger level, or when it gets empty in case that the fifo did not get filled over the trigger level on last re-load. table 8 below shows the selections. efr bit-4 must be set to ?1? before these bits can be accessed. fcr[7:6]: receive fifo trigger select (?00? = default, rx trigger level =1) these 2 bits are used to se t the trigger level for the receive fifo. th e uart will issue a rece ive interrupt when the number of the characters in the fifo crosses the trigger level. table 8 shows the selections. 4.7 line control register (lcr) - read/write the line control register is used to specify the asynchronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmitted or received. t able 8: t ransmit and r eceive fifo t rigger l evel s election fcr b it -7 fcr b it -6 fcr b it -5 fcr bit -4 r eceive t rigger l evel t ransmit t rigger l evel c ompatibility 0 0 1 1 0 1 0 1 1 (default) 4 8 14 16c580 and 16l580 compati - ble. 0 0 1 1 0 1 0 1 1 (default) 4 8 14 16c550, 16c580, 16c554, 16c2550 and 16c2552 compat - ible bit-1 bit-0 w ord length 0 0 5 (default) 0 1 6 1 0 7 1 1 8
xr16l580 29 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bi t in conjunction with the programmed word length. lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the pa rity bit is a simple way used in communications for data integrity check. see table 9 for parity selection summary below. ? logic 0 = no parity. ? logic 1 = a parity bit is generated duri ng the transmission while the receiver checks for parity error of the data character received. lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to a logi c 1, lcr bit-4 selects the even or odd parity format. ? logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted character. the receiver must be programmed to check the same format (default). ? logic 1 = even parity is gen erated by forcing an even numb er of logic 1?s in the tr ansmitted character. the receiver must be programmed to check the same format. lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit- 5 selects the forced parity format. ? lcr bit-5 = logic 0, parity is not forced (default). ? lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. ? lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. bit-2 w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 (default) 1 5 1-1/2 1 6,7,8 2 t able 9: p arity selection lcr b it -5 lcr b it -4 lcr b it -3 p arity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity to mark, ?1? 1 1 1 forced parity to space, ?0?
xr16l580 30 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 lcr[6]: transmit break enable when enabled, the break control bit causes a break cond ition to be transmitted (the tx output is forced to a ?space?, logic 0, state). this co ndition remains, until disabled by setting lcr bit-6 to a logic 0. ? logic 0 = no tx break condition (default). ? logic 1 = forces the transmitter output (tx) to a ?space ?, logic 0, for alerting the remote receiver of a line break condition. lcr[7]: baud rate divisors enable baud rate generator divisor (dll/dlm) enable. ? logic 0 = data registers are selected (default). ? logic 1 = divisor latch registers are selected. 4.8 modem control register (mcr) or general purpose outputs control - read/write the mcr register is used for contro lling the serial/modem interface signal s or general pur pose inputs/outputs. mcr[0]: dtr# output the dtr# pin is a modem control outpu t. if the modem interface is not us ed, this output may be used as a general purpose output. this bit has no functionality in the 24-qfn and 28-qfn packages except in internal loopback mode. ? logic 0 = force dtr# output to a logic 1 (default). ? logic 1 = force dtr# output to a logic 0. mcr[1]: rts# output the rts# pin is a modem control output and may be used for automatic hardware flow control by enabled by efr bit-6. if the modem interface is not used, this output may be used as a general purpose output. this bit has no functionality in the 24-qfn package except in internal loopback mode. ? logic 0 = force rts# output to a logic 1 (default). ? logic 1 = force rts# output to a logic 0. mcr[2]: invert infrared rx data or op1# (legacy term) if irda mode is enabled by setting mcr[6]=1 and if efr[ 4] = 1, this bit acts as ?invert infrared rx data? command. if efr[4] = 0 or in internal loopback m ode, this bit functions lik e the op1# in the 16c550. ? logic 0 = select rx input as active-low encoded irda data (if irda mode is enabled by setting mcr[6] = 1 and efr[4] = 1) (default). ? logic 1 = select rx input as active-high encoded irda da ta (if mcr[6] = 1 and efr[4] = 1). in this mode, this bit is write-only. in the internal loopback mode, this bi t controls the state of the modem in put ri# bit in the msr register as shown in figure 14 . mcr[3]: int output enable or op2# (legacy term) this bit enables and disables the operation of interrup t output, int in the intel mode. it has no function in the motorola mode. ? logic 0 = int output disabled (three state mode) (default). ? logic 1 = int output enabled (active mode). in the internal loopback mode, this bit functions like the op2# in the 16c550 and is used to set the state of the modem input cd# bit in the msr register.
xr16l580 31 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave mcr[4]: internal loopback enable ? logic 0 = disable loopback mode (default). ? logic 1 = enable local loopback mode, see loopback section and figure 14 . mcr[5]: xon-any enable ? logic 0 = disable xon-any function (for 16c550 compat ibility, default). ? logic 1 = enable xon-any function. in this mode, any rx character re ceived will resume transmit operation. the rx character will be loaded into the rx fifo, unless the rx characte r is an xon or xo ff character and the l580 is programmed to use the xon/xoff flow control. mcr[6]: infrared encoder/decoder enable ? logic 0 = enable the standard modem receive an d transmit input/output interface (default). ? logic 1 = enable infrared irda receive and transmit inputs/outputs. the tx/rx output/input are routed to the infrared encoder/decoder. the data input and output levels conform to the irda infrared interface requirement. while in this mode, the infrared tx ou tput will be a logic 0 duri ng idle data conditions. mcr[7]: brg clock prescaler select ? logic 0 = divide by one. the input clock from the crystal or external clock is fed directly to the programmable baud rate generator without further modification, i.e., divide by one (default). ? logic 1 = divide by four. the prescaler divides the input clock from the crystal or external clock by four and feeds it to the programmable baud rate generator, hence, data rates get reduced 4 times. 4.9 line status register (lsr) - read only this register provides the status of data transfers between the uart and the host. lsr[0]: receive data ready indicator ? logic 0 = no data in receive holding register or fifo (default). ? logic 1 = data has been received and is save d in the receive holding register or fifo. lsr[1]: receiver overrun flag ? logic 0 = no overrun error (default). ? logic 1 = overrun error. a data overrun error condition occurred in the receive shift register. this happens when additional data arrives while the fi fo is full. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. lsr[2]: receive data parity error flag ? logic 0 = no parity error (default). ? logic 1 = parity error. the receive character in rhr does not have correct parity information and is suspect. this error is associated with the char acter available for reading in rhr. lsr[3]: receive data framing error flag ? logic 0 = no framing error (default). ? logic 1 = framing error. the receive character did not hav e a valid stop bit(s). this error is associated with the character available for reading in rhr.
xr16l580 32 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 lsr[4]: receive break flag ? logic 0 = no break condition (default). ? logic 1 = the receiver received a break signal (rx was a logic 0 for at least one character frame time). in the fifo mode, only one break character is loaded into the fifo. the break indication remains until the rx input returns to the idle condition, ?mark? or logic 1. lsr[5]: transmit holding register empty flag this bit is the transmit holding register empty indicator. the thr bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to th e transmit shift register. the bit is reset to logic 0 concurrently with the data loading to the transmit holding r egister by the host. in the fifo mode this bit is set when the transmit fifo is empty, it is cleared when the transmit fifo contains at least 1 byte. lsr[6]: thr and tsr empty flag this bit is set to a logic 1 whenever the transmitter goes idle. it is set to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bi t is set to a logic 1 whenever the transmit fifo and transmit shift register are both empty. lsr[7]: receive fifo data error flag ? logic 0 = no fifo error (default). ? logic 1 = a global indicator for the sum of all error bits in the rx fifo. at least one parity error, framing error or break indication is in the fifo data. this bit clears when there is no more error(s) in any of the bytes in the rx fifo. 4.10 modem status register (msr) - read only this register provides the current state of the modem interf ace input signals. lower four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a signal from the modem changes state. these bits may be used for general purpose inputs when they are not used with modem signals. msr[0]: delta cts# input flag ? logic 0 = no change on cts# input (default). ? logic 1 = the cts# input has changed state since the la st time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[1]: delta dsr# input flag ? logic 0 = no change on dsr# input (default). ? logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[2]: delta ri# input flag ? logic 0 = no change on ri# input (default). ? logic 1 = the ri# input has changed from a logic 0 to a logic 1, ending of the ringi ng signal. a modem status interrupt will be ge nerated if msr in terrupt is enabled (ier bit-3). msr[3]: delta cd# input flag ? logic 0 = no change on cd# input (default). ? logic 1 = indicates that the cd# input has changed st ate since the last time it was monitored. a modem status interrupt will be generated if ms r interrupt is enab led (ier bit-3).
xr16l580 33 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave msr[4]: cts input status cts# pin may function as automatic hardware flow control signal input if it is enabled and selected by auto cts (efr bit-7). auto cts flow contro l allows starting and stopping of local data transmissions based on the modem cts# signal. a logic 1 on the cts# pin will stop uart transmitter as soon as the current character has finished transmission, and a logic 0 will resume data transmission. norma lly msr bit-4 bit is the compliment of the cts# input. however in the loopback mode, this bit is equivalent to the rts# bit in the mcr register. the cts# input may be used as a general purpose input when the modem interface is not used. msr[5]: dsr input status dsr# (active high, logical 1). normally this bit is the compliment of the dsr# input. in the loopback mode, this bit is equivalent to the dtr# bit in the mcr register. the dsr# input may be used as a general purpose input when the modem interface is not used. msr[6]: ri input status ri# (active high, logical 1). no rmally this bit is the compliment of the ri # input. in the loopback mode this bit is equivalent to bit-2 in the mcr register. the ri# i nput may be used as a general purpose input when the modem interface is not used. msr[7]: cd input status cd# (active high, logical 1). normally this bit is the co mpliment of the cd# input. in the loopback mode this bit is equivalent to bit-3 in the mcr register. the cd# i nput may be used as a general purpose input when the modem interface is not used. 4.11 scratchpad register (spr) - read/write this is a 8-bit general purpose register for the user to store temporary data. the content of this register is preserved during sleep mode but becomes 0xff (default) after a reset or a power off-on cycle. 4.12 baud rate generator registers (dll and dlm) - read/write the concatenation of the contents of dlm and dll gives the 16-bit divisor value which is used to calculate the baud rate: ? baud rate = (clock frequency / 16) / divisor see mcr bit-7 and the baud rate table also. 4.13 device identification register (dvid) - read only this register contains the device id (0x01 for xr16l580). prior to reading this register, dll and dlm should be set to 0x00. 4.14 device revision register (drev) - read only this register contains the device revision information. for example, 0x01 means revision a. prior to reading this register, dll and dlm should be set to 0x00. 4.15 enhanced feature register (efr) enhanced features are enabled or disabled using this register. bit 0-3 provide si ngle or dual consecutive character software flow control selection (see table 10 ). when the xon1 and xon2 and xoff1 and xoff2 modes are selected, the double 8-bit words are concatenated in to two sequential characters. caution: note that whenever changing the tx or rx flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. efr[3:0]: software flow control select single character and dual sequential characters software flow control is supported. combinations of software flow control can be selected by programming these bits.
xr16l580 34 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 efr[4]: enhanced function bits enable enhanced function control bit. this bit enables ier bits 4- 7, isr bits 4-5, fcr bits 4- 5, mcr bits 2, 5, 6 and 7 to be modified. after modifying any enhanced bits, efr bit-4 can be set to a logic 0 to latch the new values. this feature prevents legacy software from altering or overwriting the enhanced functions once set. normally, it is recommended to leave it enabled, logic 1. ? logic 0 = modification disable/latch en hanced features. ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 2, 5-7 are saved to retain the user settings. after a reset, the ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 2, 5-7 are set to a logic 0 to be compatible with st16c550 mode (default). ? logic 1 = enables the above-mentioned regist er bits to be modified by the user. efr[5]: special character detect enable ? logic 0 = special character detect disabled (default). ? logic 1 = special character detect enabled. the ua rt compares each incoming receive character with data in xoff-2 register. if a match exists, the receive data will be transfer red to fifo and isr bit-4 will be set to indicate detection of the special character. bit-0 co rresponds with the lsb bit of the receive character. if flow control is set for comparing xon1, xo ff1 (efr [1:0]= ?10?) then flow control and special character work normally. however, if flow control is set for comparing xon2, xoff2 (efr[1:0]= ?01?) then flow control works normally, but xoff2 will not go to the fifo, and will g enerate an xoff interrupt and a special character interrupt, if enabled via ier bit-5. t able 10: s oftware f low c ontrol f unctions efr bit -3 c ont -3 efr bit -2 c ont -2 efr bit -1 c ont -1 efr bit -0 c ont -0 t ransmit and r eceive s oftware f low c ontrol 0 0 0 0 no tx and rx flow control (default and reset) 0 0 x x no transmit flow control 1 0 x x transmit xon1, xoff1 0 1 x x transmit xon2, xoff2 1 1 x x transmit xon1 and xon2, xoff1 and xoff2 x x 0 0 no receive flow control x x 1 0 receiver compares xon1, xoff1 x x 0 1 receiver compares xon2, xoff2 1 0 1 1 transmit xon1, xoff1 receiver compares xon1 or xon2, xoff1 or xoff2 0 1 1 1 transmit xon2, xoff2 receiver compares xon1 or xon2, xoff1 or xoff2 1 1 1 1 transmit xon1 and xon2, xoff1 and xoff2, receiver compares xon1 and xon2, xoff1 and xoff2 0 0 1 1 no transmit flow control, receiver compares xon1 and xon2, xoff1 and xoff2
xr16l580 35 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave efr[6]: auto rts flow control enable this bit has no functionality in the 24-qfn package. rts# output may be used for hardware flow control by setting efr bit-6 to logic 1. when auto rts is selected, an interrupt will be generated when the receive fifo is fi lled to the programm ed trigger level and rts de-asserts to a logic 1 at one tr igger level above the prog rammed trigger level. rts# will return to a logic 0 when fifo data falls below one trigger level below t he programmed trigger level. the rts# output must be asserted (logic 0) before the auto rts can take effect . rts# pin will function as a general pur pose output when hardware flow control is disabled. ? logic 0 = automatic rts flow control is disabled (default). ? logic 1 = enable automatic rts flow control. efr[7]: auto cts flow control enable this bit has no functionality in the 24-qfn package. automatic cts flow control. ? logic 0 = automatic cts flow control is disabled (default). ? logic 1 = enable automatic cts flow control. data tr ansmission stops when cts# input de-asserts to logic 1. data transmission resumes when cts# returns to a logic 0. 4.16 software flow control registers (xoff1, xoff2, xon1, xon2) - write only these registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2. for more details, refer to ?section 2.15, auto xon/xoff (software) flow control? on page 18 .
xr16l580 36 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 t able 11: uart reset conditions for channel a and b registers reset state dlm and dll bits 15-0 = 0x0001. resets upon power up only and not when only the reset pin is asserted. rhr bits 7-0 = 0xxx thr bits 7-0 = 0xxx ier bits 7-0 = 0x00 fcr bits 7-0 = 0x00 isr bits 7-0 = 0x01 lcr bits 7-0 = 0x00 mcr bits 7-0 = 0x00 lsr bits 7-0 = 0x60 msr bits 3-0 = logic 0 bits 7-4 = logic levels of the inputs inverted spr bits 7-0 = 0xff efr bits 7-0 = 0x00 xon1 bits 7-0 = 0x00 xon2 bits 7-0 = 0x00 xoff1 bits 7-0 = 0x00 xoff2 bits 7-0 = 0x00 i/o signals reset state tx logic 1 rts# logic 1 (not available in 24-qfn package) dtr# logic 1 (not available in 24-qfn and 28-qfn packages) int three-state condition
xr16l580 37 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave absolute maximum ratings power supply range 7 volts voltage at any pin gnd-0.3 v to 7 v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw typical package thermal resistance data ( margin of error: 15% ) thermal resistance (48-tqfp) theta-ja =59 o c/w, theta-jc = 16 o c/w thermal resistance (32-qfn) theta-ja = 40 o c/w, theta-jc = 13 o c/w dc electrical characteristics u nless otherwise noted : ta=-40 o to +85 o c, v cc =2.97 - 5.5v s ymbol p arameter l imits 3.3v m in m ax l imits 5.0v m in m ax u nits c onditions v ilck clock input low level -0.3 0.6 -0.5 0.6 v v ihck clock input high level 2.4 vcc 3.0 vcc v v il input low voltage -0.3 0.8 -0.5 0.8 v v ih input high voltage 2.0 5.5 2.2 5.5 v v ol output low voltage 0.4 0.4 v v i ol = 6 ma i ol = 4 ma v oh output high voltage 2.0 2.4 v v i oh = -6 ma i oh = -1 ma i il input low leakage current 10 10 ua see test 1a i ih input high leakage current 10 10 ua see test 1b c in input pin capacitance 5 5 pf i cc power supply current 2 3 ma i sleep / i pwrsv sleep / power-save current (16 and 68 modes, qfn packages) 15 30 ua see test 2 i sleep / i pwrsv sleep / power-save current (16 mode, 48-tqfp package) 90 150 ua see test 2 i sleep / i pwrsv sleep / power-save current (68 mode, 48-tqfp package) 180 300 ua see test 2
xr16l580 38 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 test 1a: for 48-tqfp package only: the 16/68# pin has an internal pull-up resistor, so the input leakage current is -80ua max. test 1b: for 48-tqfp package only: the pwrsave pin has an internal pull-down resistor, so the input leakage current is 80ua max. test 2: the following inputs must rema in steady at vcc or gnd state to mi nimize sleep current: a0-a2, d0-d7, ior#, iow# (r/w#), cs# and all modem inputs. also, r xa and rxb inputs must idle at logic 1 state while asleep. floating inputs may result in sleep currents in the ma range. the 48-tqfp package has a higher current because of the internal pull-up and pull-down resistors on the 16/68# and pwrsave pins respectively. for power-save, the uart internally isolates all of these inputs (except the modem inputs, 16/68# and reset pins) therefore eliminating any unnecessary external buffers to keep the inputs steady. see?power-save feature? on page 20. to achieve minimum power drain, the volt age at any of the inputs of the l580 should not be lower than its vcc supply. dc electrical characteristics u nless otherwise noted : ta=-40 o to +85 o c, v cc =1.62 - 2.75v s ymbol p arameter l imits 1.8v m in m ax l imits 2.5v m in m ax u nits c onditions v ilck clock input low level -0.3 0.6 -0.3 0.6 v v ihck clock input high level ?? vcc 1.8 vcc v v il input low voltage -0.3 0.5 -0.3 0.5 v v ih input high voltage ?? 5.5 1.8 5.5 v v ol output low voltage ?? 0.4 v v i ol = 2 ma i ol = v oh output high voltage ?? 1.8 v v i oh = -400 ua i oh = i il input low leakage current 10 10 ua see test 1a i ih input high leakage current 10 10 ua see test 1b c in input pin capacitance 5 5 pf i cc power supply current 0.5 1 ma i sleep / i pwrsv sleep / power-save current (16 and 68 modes, qfn packages) 3 6 ua see test 2 i sleep / i pwrsv sleep / power-save current (16 mode, 48-tqfp package) 30 65 ua see test 2 i sleep / i pwrsv sleep / power-save current (68 mode, 48-tqfp package) 65 130 ua see test 2
xr16l580 39 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave ac electrical characteristics u nless otherwise noted : ta=-40 o to +85 o c, v cc =2.97 - 5.5v, 70 p f load where applicable s ymbol p arameter l imits 3.3 m in m ax l imits 5.0 m in m ax u nit - crystal frequency 20 24 mhz osc external clock frequency 33 50 mhz clk external clock low/high time 15 10 ns t as address setup time (16 mode) 5 10 ns t ah address hold time (16 mode) 0 0 ns t cs chip select width (16 mode) 50 30 ns t rd ior# strobe width (16 mode) 50 30 ns t dy read cycle delay (16 mode) 50 30 ns t rdv data access time (16 mode) 50 25 ns t dd data disable time (16 mode) 0 20 0 20 ns t wr iow# strobe width (16 mode) 50 30 ns t dy write cycle delay (16 mode) 50 30 ns t ds data setup time (16 mode) 15 12 ns t dh data hold time (16 mode) 3 5 ns t ads address setup (68 mode) 5 10 ns t adh address hold (68 mode) 0 0 ns t rws r/w# setup to cs# (68 mode) 10 10 ns t rda read data access (68 mode) 50 25 ns t rdh read data disable time (68 mode) 20 20 ns t wds write data setup (68 mode) 15 12 ns t wdh write data hold (68 mode) 3 5 ns t rwh cs# de-asserted to r/w# de-asserted (68 mode) 10 10 ns t csl cs# width (68 mode) 50 30 ns t csd cs# cycle delay (68 mode) 50 30 ns t wdo delay from iow# to output 75 50 ns t mod delay to set interrupt from modem input 75 50 ns t rsi delay to reset interrupt from ior# 75 50 ns t ssi delay from stop to set interrupt 1 1 bclk t rri delay from ior# to reset interrupt 75 50 ns t si delay from stop to interrupt 75 50 ns t int delay from initial int reset to transmit start 8 24 8 24 bclk t wri delay from iow# to reset interrupt 75 50 ns t rst reset pulse width 40 40 ns n baud rate divisor 1 2 16 -1 1 2 16 -1 - bclk baud clock 16x of data rate hz
xr16l580 40 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 ac electrical characteristics u nless otherwise noted : ta=-40 o to +85 o c, v cc =1.62 - 2.75v, 70 p f load where applicable s ymbol p arameter l imits 1.8 m in m ax l imits 2.5 m in m ax u nit - crystal frequency 18 mhz osc external clock frequency (with 2k pull-up on xtal2) 12 24 mhz osc external clock frequency (with xtal2 floating) 2? 18 mhz clk external clock low/high time 20 ns t as address setup time (16 mode) 5 ns t ah address hold time (16 mode) 0 0 ns t cs chip select width (16 mode) 100 ns t rd ior# strobe width (16 mode) 100 ns t dy read cycle delay (16 mode) 100 ns t rdv data access time (16 mode) 75 ns t dd data disable time (16 mode) 0 30 ns t wr iow# strobe width (16 mode) 100 ns t dy write cycle delay (16 mode) 100 ns t ds data setup time (16 mode) 25 ns t dh data hold time (16 mode) 3 ns t ads address setup (68 mode) 5 ns t adh address hold (68 mode) 0 ns t rws r/w# setup to cs# (68 mode) 10 ns t rda read data access (68 mode) 75 ns t rdh read data disable time (68 mode) 30 ns t wds write data setup (68 mode) 25 ns t wdh write data hold (68 mode) 3 ns t rwh cs# de-asserted to r/w# de-asserted (68 mode) 10 ns t csl cs# width (68 mode) 100 ns t csd cs# cycle delay (68 mode) 100 ns t wdo delay from iow# to output 150 ns t mod delay to set interrupt from modem input 150 ns t rsi delay to reset interrupt from ior# 150 ns t ssi delay from stop to set interrupt 1 1 bclk t rri delay from ior# to reset interrupt 150 ns t si delay from stop to interrupt 150 ns t int delay from initial int reset to transmit start 8 24 8 24 bclk t wri delay from iow# to reset interrupt 150 ns t rst reset pulse width 40 40 ns n baud rate divisor 1 2 16 -1 1 2 16 -1 - bclk baud clock 16x of data rate hz
xr16l580 41 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave f igure 15. c lock t iming f igure 16. m odem i nput /o utput t iming osc clk clk external clock iow# rts# dtr# cd# cts# dsr# int ior# ri# t wdo t mod t mod t rsi t mod activ e change of state change of state activ e activ e activ e change of state change of state change of state activ e activ e
xr16l580 42 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 f igure 17. 16 m ode (i ntel ) d ata b us r ead t iming f igure 18. 16 m ode (i ntel ) d ata b us w rite t iming t as t dd t ah t rd t rdv t dy t dd t rdv t ah t as t cs valid address valid address valid data valid data a0- a2 cs# ior# d0-d7 rdtm t cs t rd 16write t as t dh t ah t wr t ds t dy t dh t ds t ah t as t cs valid address valid address valid data valid data a0- a2 cs# iow# d0-d7 t cs t wr
xr16l580 43 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave f igure 19. 68 m ode (m otorola ) d ata b us r ead t iming f igure 20. 68 m ode (m otorola ) d ata b us w rite t iming 68read t ads t rdh t adh t csl t rda t csd t rws valid address valid address valid data a0-a2 cs# r/w# d0-d7 t rwh valid data 68write t ads t adh t csl t wds t csd t rws valid address valid address valid data a0-a2 cs# r/w# d0-d7 t rwh valid data t wdh
xr16l580 44 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 f igure 21. r eceive r eady i nterrupt t iming [n on -fifo m ode ] f igure 22. t ransmit r eady i nterrupt t iming [n on -fifo m ode ] rx int d0:d7 start bit d0:d7 stop bit d0:d7 1 byte in rhr 1 byte in rhr 1 byte in rhr rxnfm t ssr t ssr t ssr ior# t rr t rr t rr (reading data out of rhr) tx int* d0:d7 start bit d0:d7 stop bit d0:d7 txnonfifo t wri t wri t wri t srt t srt t srt *int is cleared when the isr is read or when data is loaded into the thr. isr is read isr is read isr is read (unloading) ier[1] enabled iow# (loading data into thr)
xr16l580 45 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave f igure 23. r eceive r eady i nterrupt t iming [fifo m ode ] f igure 24. t ransmit r eady i nterrupt t iming [fifo m ode ] rx int d0:d7 s t ssr rxintdma# rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t ssi ior# t rri (reading data out of rx fifo) tx int* tx int d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri last data byte transmitted tx fifo fills up to trigger level tx fifo drops below trigger level tx fifo empty t t s t si isr is read ier[1] enabled isr is read iow# (loading data into fifo) *int is cleared when the isr is read or when tx fifo fills up to the trigger level.
xr16l580 46 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 package dimensions (48 pin tqfp - 7 x 7 x 1 mm ) note: the control dimension is the millimeter column inches millimeters symbol min max min max a 0.039 0.047 1.00 1.20 a1 0.002 0.006 0.05 0.15 a2 0.037 0.041 0.95 1.05 b 0.007 0.011 0.17 0.27 c 0.004 0.008 0.09 0.20 d 0.346 0.362 8.80 9.20 d1 0.272 0.280 6.90 7.10 e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 a 0 7 0 7 36 25 24 13 1 1 2 37 48 d d 1 d d 1 b e a 2 a 1 a seating plane l c
xr16l580 47 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave package dimensions (32 pin qfn - 5 x 5 x 0.9 mm ) note: the control dimension is in millimeter. inches millimeters symbol min max min max a 0.031 0.039 0.80 1.00 a1 0.000 0.002 0.00 0.05 a3 0.006 0.010 0.15 0.25 d 0.193 0.201 4.90 5.10 d2 0.138 0.150 3.50 3.80 b 0.007 0.012 0.18 0.30 e 0.0197 bsc 0.50 bsc l 0.012 0.020 0.35 0.45 k 0.008 - 0.20 - note: the actual center pad is metallic and the size (d2) is device-dependent with a typical tolerance of 0.3mm
xr16l580 48 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 package dimensions (28 pin qfn - 5 x 5 x 0.9 mm ) note: the control dimension is in millimeter. inches millimeters symbol min max min max a 0.031 0.039 0.80 1.00 a1 0.000 0.002 0.00 0.05 a3 0.006 0.010 0.15 0.25 d 0.193 0.201 4.90 5.10 d2 0.138 0.150 3.50 3.80 b 0.007 0.012 0.18 0.30 e 0.0197 bsc 0.50 bsc l 0.014 0.018 0.35 0.45 k 0.008 - 0.20 - note: the actual center pad is metallic and the size (d2) is device-dependent with a typical tolerance of 0.3mm
xr16l580 49 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave package dimensions (24 pin qfn - 4 x 4 x 0.9 mm ) note: the control dimension is in millimeter. inches millimeters symbol min max min max a 0.031 0.039 0.80 1.00 a1 0.000 0.002 0.00 0.05 a3 0.006 0.010 0.15 0.25 d 0.154 0.161 3.90 4.10 d2 0.098 0.110 2.50 2.80 b 0.007 0.012 0.18 0.30 e 0.0197 bsc 0.50 bsc l 0.014 0.018 0.35 0.45 k 0.008 - 0.20 - note: the actual center pad is metallic and the size (d2) is device-dependent with a typical tolerance of 0.3mm
50 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infr ingement. charts and schedules contai ned here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assuranc es to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) th e user assumes all such ris ks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2007 exar corporation datasheet may 2007. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. xr16l580 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 revision history d ate r evision d escription november 2003 rev 1.0.0 final datasheet. updated dc and ac electical characteristics tables. december 2003 rev 1.1.0 added missing 16 mode (intel) data bus read timing diagram. january 2004 rev 1.2.0 updated dc electrical characteristics to include icc and sleep/power-save current for final production devices of 48-tqfp and 32-qfn packages. october 2004 rev 1.3.0 corrected 32-qfn package dimension descriptions. added gnd center pad pin descrip - tion. february 2005 rev 1.3.1 corrected 32-qfn pinout on page 2 (pinout with 16/68# pin connected to gnd is for motorola bus mode). august 2005 rev 1.4.0 added 28-qfn and 24-qfn packages. the modem pins dtr#, dsr#, ri# and cd# are not available in the 28-qfn package. the modem pins rts#, cts#, dtr#, dsr#, ri# and cd# are not available in the 24-qfn package. may 2007 rev 1.4.1 updated qfn package dimensions drawing to show minimum "k" parameter.
xr xr16l580 rev. 1.4.1 smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave i table of contents general description........ ................. ................ ................ ............... .............. ........... 1 a pplications ............................................................................................................................... ................ 1 f eatures ............................................................................................................................... ...................... 1 f igure 1. b lock d iagram ............................................................................................................................... .............................. 1 f igure 2. p ackages and p in o ut (24, 28 and 32- pin qfn p ackages )........................................................................................ 2 f igure 3. p ackages and p in o ut (48-tqfp p ackage )................................................................................................................ 3 ordering information ............................................................................................................................... .3 pin descriptions ............ ................ ................ ................. ................ ................. ........... 4 1.0 product description ..................................................................................................... ............... 7 2.0 functional descriptions ................................................................................................. ........... 8 2.1 cpu interface ........................................................................................................... .................................. 8 f igure 4. xr16l580 t ypical i ntel /m otorola d ata b us i nterconnections ............................................................................. 8 2.2 5-volt tolerant inputs .... .............. .............. .............. .............. .............. .............. .......... ......................... 9 2.3 device hardware reset ..... .............. .............. .............. .............. .............. .............. .......... ....................... 9 2.4 device identification and revision ........... ........................................................................... .............. 9 2.5 internal registers ...................................................................................................... ............................. 9 2.6 dma mode ................................................................................................................ ...................................... 9 2.7 int (irq#) output ....................................................................................................... .................................. 9 t able 1: int (irq#) p in o peration for t ransmitter ................................................................................................................. 9 t able 2: int (irq#) p in o peration f or r eceiver .................................................................................................................... 10 2.8 crystal or external clock in put .......... .............. .............. .............. .............. .............. ......... .......... 10 f igure 5. t ypical c rystal connections ............................................................................................................................... .... 10 f igure 6. e xternal c lock c onnection for e xtended d ata r ate .......................................................................................... 11 2.9 programmable baud rate gene rator ............... .............. .............. ........... ........... ........... ........... ... 11 f igure 7. b aud r ate g enerator and p rescaler ..................................................................................................................... 11 t able 3: t ypical data rates with a 14.7456 mh z crystal or external clock ...................................................................... 12 2.10 transmitter ....... .............. .............. .............. .............. ........... ........... ........... ............ ................................. 13 2.10.1 transmit holding register (thr) - write only.......................................................................... ............. 13 2.10.2 transmitter operatio n in non-fifo mode ................................................................................ ................ 13 f igure 8. t ransmitter o peration in non -fifo m ode .............................................................................................................. 13 2.10.3 transmitter operation in fifo mode .................................................................................... ..................... 13 f igure 9. t ransmitter o peration in fifo and f low c ontrol m ode ..................................................................................... 14 2.11 receiver ............................................................................................................... ..................................... 14 2.11.1 receive holding register (rhr) - read-only ............................................................................ .............. 14 f igure 10. r eceiver o peration in non -fifo m ode .................................................................................................................. 15 f igure 11. r eceiver o peration in fifo and a uto rts f low c ontrol m ode ....................................................................... 15 2.12 auto rts (hardware ) flow control .............. .............. .............. ........... ........... ............ .......... ...... 16 2.13 auto rts hysteresis ................................................................................................... ........................ 16 2.14 auto cts flow control ................................................................................................. .................... 16 f igure 12. a uto rts and cts f low c ontrol o peration (n ot a vailable in 24-qfn p ackage )........................................... 17 2.15 auto xon/xoff (software) flow control ................................................................................. . 18 t able 4: a uto x on /x off (s oftware ) f low c ontrol ............................................................................................................... 18 2.16 special character detect .. .............. .............. .............. .............. .............. ........... ........... ................. 18 2.17 infrared mode ..... .............. .............. .............. .............. .............. ........... ........... ......... .............................. 19 f igure 13. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding .......................................................................... 19 2.18 sleep mode with wake-up interrupt and powe r-save feature ............ ............ ........... ..... 20 2.18.1 sleep mode ............................................................................................................ ............................................... 20 2.18.2 power-save feature .................................................................................................... .................................... 20 2.19 internal loopback ..................................................................................................... ......................... 21 f igure 14. i nternal l oop b ack ............................................................................................................................... .................. 21 3.0 uart internal registers ................................................................................................. .......... 22 t able 5: uart internal registers................................................................................................... ................................. 22 t able 6: internal registers description. s haded bits are enabled when efr b it -4=1.......................................... 23 4.0 internal register descriptions .......................................................................................... .. 24 4.1 receive holding register (rhr) - read- only . .............. .............. .............. ........... ........... ............ .. 24 4.2 transmit holding register (thr) - write-only ............................................................................ 24 4.3 baud rate generator divisors (dll and dlm) - read/wri te ......... .............. ............ ........... ..... 24 4.4 interrupt enable register (ier ) - read/write .......... .............. .............. .............. .............. .......... . 24 4.4.1 ier versus receive fifo interrupt mode operation ....................................................................... ...... 24
xr16l580 xr smallest 2.25v to 5.5v uart wi th 16-byte fifo and powersave rev. 1.4.1 ii 4.4.2 ier versus receive/transmit fifo polled mode operation ................................................................ 25 4.5 interrupt status register (isr) - read-only ............................................................................. .. 26 4.5.1 interrupt generation: .................................................................................................. .................................... 26 4.5.2 interrupt clearing: .................................................................................................... ....................................... 26 t able 7: i nterrupt s ource and p riority l evel ....................................................................................................................... 27 4.6 fifo control register (fcr) - write-only ................................................................................ ...... 27 t able 8: t ransmit and r eceive fifo t rigger l evel s election .............................................................................................. 28 4.7 line control register (lcr) - read/write ................................................................................ ...... 28 t able 9: p arity selection ............................................................................................................................... ........................... 29 4.8 modem control register (mcr) or gene ral purpose outputs control - read/write 30 4.9 line status register (lsr) - read only .................................................................................. ......... 31 4.10 modem status register (msr) - read only ................................................................................ .. 32 4.11 scratchpad register (spr) - read/write ................................................................................. .... 33 4.12 baud rate generator registers (dll and dlm) - read/write ...... ........... ........... ........... ....... 33 4.13 device identification register (dvid) - read only .................................................................... 3 3 4.14 device revision register (drev) - read only ............................................................................ .. 33 4.15 enhanced feature register (e fr) ............ .............. .............. .............. ........... ........... ........... .......... 33 t able 10: s oftware f low c ontrol f unctions ........................................................................................................................ 34 4.16 software flow control registers (xoff1, xoff2, xon1, xon2) - write only ................ 35 t able 11: uart reset conditions for channel a and b................................................................................ ............ 36 absolute maximum ratings........... ................ ................ ............... .............. ...........37 typical package thermal resistance data (margin of error: 15%) 37 dc e lectrical c haracteristics ..............................................................................................................37 dc e lectrical c haracteristics ..............................................................................................................38 ac e lectrical c haracteristics ..............................................................................................................39 unless otherwise noted: ta=-40o to +85oc, vcc=2.97 - 5.5v, 70 pf load where applicable ................................... 39 ac e lectrical c haracteristics ..............................................................................................................40 unless otherwise noted: ta=-40o to +85oc, vcc=1.62 - 2.75v, 70 pf load where applicable ................................. 40 f igure 15. c lock t iming ............................................................................................................................... .............................. 41 f igure 16. m odem i nput /o utput t iming ............................................................................................................................... ..... 41 f igure 17. 16 m ode (i ntel ) d ata b us r ead t iming ................................................................................................................... 42 f igure 18. 16 m ode (i ntel ) d ata b us w rite t iming .................................................................................................................. 42 f igure 19. 68 m ode (m otorola ) d ata b us r ead t iming .......................................................................................................... 43 f igure 20. 68 m ode (m otorola ) d ata b us w rite t iming ......................................................................................................... 43 f igure 21. r eceive r eady i nterrupt t iming [n on -fifo m ode ] ............................................................................................... 44 f igure 22. t ransmit r eady i nterrupt t iming [n on -fifo m ode ] ............................................................................................. 44 f igure 23. r eceive r eady i nterrupt t iming [fifo m ode ] ....................................................................................................... 45 f igure 24. t ransmit r eady i nterrupt t iming [fifo m ode ] ..................................................................................................... 45 package dimensions (48 pin tqfp - 7 x 7 x 1 mm)... ................ ................. ...........46 package dimensions (32 pin qfn - 5 x 5 x 0.9 mm)... ............... ................. ...........47 package dimensions (28 pin qfn - 5 x 5 x 0.9 mm)... ............... ................. ...........48 package dimensions (24 pin qfn - 4 x 4 x 0.9 mm)... ............... ................. ...........49 r evision h istory ............................................................................................................................... ........50 t able of c ontents ................ ................. ................ ................ ............... .............. .............. i

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